请帮我注释这个VHDL程序

来源：百度知道 编辑：UC知道 时间：2024/07/02 12:04:34
每一句都要注释。谢谢啦~

library ieee ;
use ieee.std_logic_1164.all;

entity mylight is
port (start : in std_logic;
stop : in std_logic;
clk:in std_logic;
shift_left : in std_logic;
Q : out std_logic_vector(7 downto 0)

);
end mylight;

architecture behavior of mylight is

signal lights : std_logic_vector(7 downto 0);
begin
process(clk, start, stop, shift_left)
begin
if (start = '0' or stop = '1') then lights <= (others => '1');
elsif (clk'event and clk = '1') then
if (shift_left = '1') then
lights <= lights(6 downto 0) & '0';
else
lights <= '0' & lights(7 downto 1);
end if;
end if;
end process;

Q <= lights;

end behavior;

library ieee ;
use ieee.std_logic_1164.all;

entity mylight is
port (start : in std_logic;
stop : in std_logic;
clk:in std_logic;
shift_left : in std_logic;
Q : out std_logic_vector(7 downto 0)

);
end mylight;

architecture behavior of mylight is

signal lights : std_logic_vector(7 downto 0);
begin
process(clk, start, stop, shift_left)
begin
if (start = '0' or stop = '1') then lights <= (others => '1');
elsif (clk'event and clk = '1') then
if (shift_left = '1') then
lights <= lights(6 downto 0) & '0';
else
lights <= '0' & lights(7 downto 1);
end if;
end if;
end process;

Q <= lights;

end behavior;
端口就不说了
程序一开始 判断start stop 然后点亮led
每个时钟下判断shift_left 真 左移一位 低位灭
假 右移一位 高灭