哪里有加法或是减法计数器的verilog的源代码与激励程序

我编写的可预置可循环的加减计数器
module counter(clk,clear,n,s,q);
output[15:0] q;
input clk,clear,s;
input[15:0] n;
reg[15:0] q;
always@(n) q<=n;
always @(posedge clk)
begin
if (clear)
q <= 0;
else
begin
if (s)
begin
if (q=={16{1'b1}}) q<={16{1'b0}};
else q=q+1;
end
else
begin
if (q=={16{1'b0}}) q<={16{1'b1}};
else q<=q-1;
end
end
end
endmodule

http://www.stcsm.gov.cn/learning/lesson/xinxi/20010802/20010802.asp