谁能给我一个数字逻辑电路设计电子钟 的设计

module digitalclock(clk,clk_1k,mode,change,turn,alert,
hour,min,sec,LD_alert,LD_hour,LD_min);
input clk,clk_1k,mode,change,turn;
output alert,LD_alert,LD_hour,LD_min;
output[7:0] hour,min,sec;
reg[7:0] hour,min,sec,hour1,min1,sec1,ahour,amin;
reg[1:0] m,fm,num1,num2,num3,num4;
reg[1:0] loop1,loop2,loop3,loop4,sound;
reg LD_hour,LD_min;
reg clk_1Hz,clk_2Hz,minclk,hclk;
reg alert1,alert2,ear;
reg count1,count2,counta,countb;
wire ct1,ct2,cta,ctb,m_clk,h_clk;

always @(posedge clk)
begin
clk_2Hz<=~clk_2Hz;
if(sound==3) begin sound<=0;ear<=1;end
//ear信号用于产生或屏蔽声音
else begin sound<=sound+1;ear<=0;end
end

always @(posedge clk_2Hz)
clk_1Hz<=~clk_1Hz;
always @(posedge mode)
begin if(m==2) m<=0;
else m<=m+1;
end
always @(posedge turn)
fm<=~fm;

always
begin
case(m)
2:begin if