UC知道max+plus2 在编译verilog hdl时出现这个问题？？
来源：百度知道 编辑：UC知道 时间：2024/07/16 13:48:29
079064189.v如下（该文件目录：d:\079064189.v）:
module myadder(
a,
b,
carry_in,
sum,
carry_out
);
input a,b,carry_in;
output sum,carry_out;
wire a,b,carry_in;
reg sum,carry_out;
reg temp;
always @(a or b carry_in)
begin
temp1=a^b;
sum=temp^carry_in;
carry_out=a&b|a&carry_in|b&carry_in;
end
end module
编译时出现如下问题：
module myadder(
a,
b,
carry_in,
sum,
carry_out
);
input a,b,carry_in;
output sum,carry_out;
wire a,b,carry_in;
reg sum,carry_out;
reg temp;
always @(a or b carry_in)
begin
temp1=a^b;
sum=temp^carry_in;
carry_out=a&b|a&carry_in|b&carry_in;
end
end module
编译时出现如下问题：
module myadder(
a,
b,
carry_in,
sum,
carry_out
);
input a,b,carry_in;
output sum,carry_out;
wire a,b,carry_in;
reg sum,carry_out;
reg temp;
always @(a or b or carry_in)
begin
temp<=a^b;
sum<=temp^carry_in;
carry_out<=a&b|a&carry_in|b&carry_in;
end
endmodule
这个可以 自己对比一下就可以发现问题了