vhdl语言实现8位算术逻辑运算器

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity minutes is

Port ( rst3,selector2,ky_2j : in STD_LOGIC;

B10 : in std_logic;

C : out std_logic;

dat30 : out std_logic_vector(7 downto 0));

end minutes;

architecture Behavioral of minutes is

signal dat31,dat32 : std_logic_vector(7 downto 0):=(others =>'0');

begin

process(rst3,B10,ky_2j)

begin

case selector2 is

when '1' =>dat32<=dat31; if ky_2j'event and ky_2j='1' then

if dat31(7 downt