maxplus II 中VHDL移位运算
来源:百度知道 编辑:UC知道 时间:2024/07/07 01:59:09
我试过在maxplus II 的VHDL环境中使用SRL和SLL操作,结果不能编译通过,连SRL运算符的颜色都没变(按理说运算符应该变蓝的),哪位能给出具体的语句或者其他的移位操作方法,先谢过了。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity minutes is
Port ( rst3,selector2,ky_2j : in STD_LOGIC;
B10 : in std_logic;
C : out std_logic;
dat30 : out std_logic_vector(7 downto 0));
end minutes;
architecture Behavioral of minutes is
signal dat31,dat32 : std_logic_vector(7 downto 0):=(others =>'0');
begin
process(rst3,B10,ky_2j)
begin
case selector2 is
when '1' =>dat32<=dat31; if ky_2j'event and ky_2j='1' then
if dat31(7 downt