求vhdl设计八位全加器的程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity add_8 is
port (a,b:in std_logic_vector(7 downto 0);
cin:in std_logic;
sum:out std_logic_vector(7 downto 0);
cout:out std_logic);
end add_8;
architecture a of add_8 is
signal s:std_logic_vector(8 downto 0);
begin
s<=('0' & a)+b+cin;
sum<=s(7 downto 0);
cout<=s(8);
end a;