UC知道帮帮忙，求电子专业英语翻译一段
来源：百度知道 编辑：UC知道 时间：2024/06/27 14:03:54
As an example of how PLD architecture affects speedperformance,
consider a generic finite state machine (a real
example of such a circuit is given in the next section). If a
FSM is to be implemented in an FPGA, then the amount of
logic feeding each state machine flip-flop must be minimized.
This follows because in FPGAs flip-flops are directly
fed by logic blocks that have relatively few inputs (typically
4 - 8). If the state machine flip-flops are fed by more logic
than will fit into a single logic block, then multiple levels of
logic blocks will be needed, and speed-performance will
decrease.For this reason, designers usually use “one-hot”
state machine encoding when targeting FPGAs, so that the
amount of logic that sets each flip-flop is minimized. Even
in a CPLD architecture, speed-performance of a state
machine can be significantly affected by state bit encoding;for example, in the Altera MAX 7000 CPLDs, flip-fl
consider a generic finite state machine (a real
example of such a circuit is given in the next section). If a
FSM is to be implemented in an FPGA, then the amount of
logic feeding each state machine flip-flop must be minimized.
This follows because in FPGAs flip-flops are directly
fed by logic blocks that have relatively few inputs (typically
4 - 8). If the state machine flip-flops are fed by more logic
than will fit into a single logic block, then multiple levels of
logic blocks will be needed, and speed-performance will
decrease.For this reason, designers usually use “one-hot”
state machine encoding when targeting FPGAs, so that the
amount of logic that sets each flip-flop is minimized. Even
in a CPLD architecture, speed-performance of a state
machine can be significantly affected by state bit encoding;for example, in the Altera MAX 7000 CPLDs, flip-fl
作为一个例子,说明PLD的结构影响speedperformance, 考虑一个通用有限状态机(一个真实的例子,这种电路是由于在下一节). 如果fsm是要落实在一个fpga, 然后金额逻辑喂养每个国家机器触发器必须降到最低. 这是因为在fpgas触发器是直接喂逻辑区块都有相对投入很少(一般为4- 8). 如果国家机器触发器是助长了更多的逻辑比将被纳入一个单一的逻辑块, 那么多层次的逻辑块将需要与高速性能将decrease.for为此, 设计者通常使用"一热"的状态机编码针对fpgas, 因此,这个数额的逻辑套,每套触发器最低. 即使是在一个CPLD的结构,速度表现了国家机器,可以大大受国家比特编码; 举例来说, 在Altera的马克斯7000cplds, 触发器是喂了5名或更少的生产条件或者ed一起运作速度比那些需要更多 超过5项. 一般 设计师希望获得最高性能的应用,需要不断考虑的细微差别,他们plds建筑.
可能是!!!