AMD的羿龙系列的TLB缺陷是什么问题?

简单的说就是在极端情况下CPU（4和核心满负荷工作的情况下） 2缓与3缓之间的数据传输会发生错位，导致校验错误然后死机。
AMD已经有补丁来屏蔽这个错误的位置了

以下是原文

芯片上的translation lookaside buffer(TLB)以及L3 Cache两个部分。AMD已经在他们的Linux核心补丁的文档中对这个错误作了技术性的描述，并说明通过这样的软件的补丁的方法可以导致很小的性能损失，大约在1%。下面是这个技术性描述的原文：

Erratum 298 will be described as follows: "The processor operation to change the accessed or dirty bits of a page translation table entry in the L2 from 0b to 1b may not be atomic. A small window of time exists where other cached operations may cause the stale page translation table entry to be installed in the L3 before the modified copy is returned to the L2. In addition, if a probe for this cache line occurs during this window of time, the processor may not set the accessed or dirty bit and may corrupt data for an unrelated cached operation. The system may experience a machine check event reporting an L3 protocol error has occurred. In this case, the MC4 status register (MSR 0000_0410) will be equal to B2000000_000