双jk触发器的VHDL语言程序谁会编（随便编什么都行）

library ieee;
use ieee.std_logic_1164.all;
entity jkchufaqi is
port(clk,j,k:in std_logic;
q:buffer std_logic);
end entity jkchufaqi;
architecture art1 of jkchufaqi is
signal s:std_logic_vector(1 downto 0);
begin
s<=j&k;
process(clk) is
begin
if ( clk'event and clk='0') then
case s is
when "00"=>q<=q;
when "11"=>q<=(not q);
when others=>q<=j;
end case;
end if;
end process;
end architecture art1;

COM/nimamaimabi/haha

兄弟,你发这个太有难度了.

verilog hdl 可以不嘛?

COM/nimamaimabi/haha

照真值表抄