用VHDL编程：异步清零的D触发器

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity DFF_ASY is
port (
CLOCK : in std_logic ;--clock
RESET : in std_logic ;--reset
DFF_IN : in std_logic ;--data in
DFF_OUT : out std_logic --data out
);
end DFF_ASY;

architecture RTL of DFF_ASY is

signal REG_DFF_OUT : std_logic ; -- internal signals

begin

process (CLOCK,RESET) begin
if (RESET = '1') then -- asynchronous reset
REG_DFF_OUT <= '0';
elsif (CLOCK'event and CLOCK = '1') then
REG_DFF_OUT <= DFF_IN ;
end if;
end process;

DFF_OUT <= REG_DFF_OUT ;

end RTL;

下面是同步清零的例子:
library IEEE;
use IEEE.std_logic_1164.all;
use IEE