求LCD的VHDL显示模块，用1602的芯片

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity LCD1602 is
Port (
CLK : in std_logic;
Reset : in std_logic;
LCD_RS : out std_logic;
LCD_RW : out std_logic;
LCD_EN : out std_logic;
data : out std_logic_vector(3 downto 0));
end LCD1602;
architecture Behavioral of LCD1602 is
type iState is (
Write_instr, --写命令字
Write_DataUP4_1, --写LCD一线高4位
Write_DataDown4_1, --写LCD一线低4位
Set_DDRamAddUp, --设置DDRam地址高4位
Set_DDRamAddDown, --设置DDRam地址低4位
Write_DataUP4_2, --写LCD二线高4位
Write_DataDown4_2 --写LCD二线低4位
);

signal State:iState;
type Ram is array(0 to 15) of std_logic_vector(7 downto 0);
constant MyRamUp:Ram:=(x"