VHDL 关于4位二进制计数器

来源：百度知道 编辑：UC知道 时间：2024/07/01 06:53:59
我编了一个4位二进制计数器，总是报错~不知哪得问题！请教一下~谢谢各位了！我写得比较麻烦~因为初学~所以希望高手们能够在我的基础上改~再次感谢~急~
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt16 is
port(clk,r,s,en:in std_logic;
d:in std_logic_vector(3 downto 0);
co:out std_logic;
q:buffer std_logic_vector(3 downto 0));
end cnt16;
architecture one of cnt16 is
begin
process(clk,r,s)
begin
if r='1' then
q<="0000";
elsif clk'event and clk='1' and s='1' then
q<=d;
end if;
if clk'event and clk='1' and en='1' and s='0' and r='0' then
q<=q+1;
end if;
if r='0' and s='0' and en='0' then
q<=q;
end if;
end process;
co<='1' when q="1111" and en='1' else '0';
end;
请详细一下~具体怎么修改？谢谢了

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt16 is
port(clk,r,s,en:in std_logic;
d:in std_logic_vector(3 downto 0);
co:out std_logic;
q:buffer std_logic_vector(3 downto 0));
end cnt16;
architecture one of cnt16 is
begin
process(clk,r,s)
begin
if r='1' then
q<="0000";
elsif clk'event and clk='1' then
if s='1' then --错误的
q<=d;
end if;
end if;
if clk'event and clk='1' then
if en='1' and s='0' and r='0' then ----错误的
q<=q+1;
end if;
end if;
if r='0' and s='0' and en='0' then
q<=q;
end if;
end process;
co<='1' when q="1111" and en='1' else '0';
end one;