VHDL语言的主从JK触发器

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY jkff1 IS
PORT (clk,j,k: IN std_logic;
q,qb: OUT std_logic);
END;
ARCHITECTURE rtl OF jkff1 IS
SIGNAL q_temp, qb_temp: std_logic;
BEGIN PROCESS (clk,j,k)
BEGIN
IF clk'event AND clk='1' THEN
IF (j=‘0’ AND k=‘1’) THEN q_temp<=‘0’;qb_temp<=‘1’;
ELSIF (j=‘1’ AND k=‘0’) THEN q_temp<=‘1’;qb_temp<=‘0’;
ELSIF (j=‘1’ AND k=‘1’) THEN
q_temp<=not q_temp;qb_temp<= not qb_temp;
ELSE q_temp<=q_temp; qb_temp<=qb_temp;
END IF;
END PROCESS;
q<=q_temp;qb<=qb_temp;
END;