VHDL语言的时钟设计的问题

来源：百度知道 编辑：UC知道 时间：2024/07/07 21:34:43
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cntm60 is
port(ci: in std_logic;
nreset: in std_logic;
load: in std_logic;
d: in std_logic_vector(7 downto 0);
clk: in std_logic;
co: out std_logic;
qh: buffer std_logic_vector(3 downto 0);
ql: buffer std_logic_vector(3 downto 0));
end entity cntm60;
architecture art of cntm60 is
begin
co<='1'when(qh="0101"and ql="1001" and ci='1')else'0';
process(clk,nreset) is
begin
if(nreset='0')then
qh<="0000";
ql<="0000";
elsif(clk'event and clk='1')then
if(load='1')then
qh<=d(7 downto 4);
ql<=d(3 downto 0);
elsif(ci='1')then
if(ql=9)then
ql<="0000&

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cntm60 is
port(ci: in std_logic; 计数使能
nreset: in std_logic; 清零端
load: in std_logic; 置数使能
d: in std_logic_vector(7 downto 0); 置数输入
clk: in std_logic; 时钟输入
co: out std_logic; 进位输出
qh: buffer std_logic_vector(3 downto 0); 计数器高位
ql: buffer std_logic_vector(3 downto 0));计数器低位
end entity cntm60;
architecture art of cntm60 is
begin
co<='1'when(qh="0101"and ql="1001" and ci='1')else'0';计数满则输出进位
process(clk,nreset) is
begin
if(nreset='0')then 清零端
qh<="0000";
ql<="0000";
elsif(clk'event and clk='1')then 脉冲上升沿有效
if(load='1')then load为1