vhdl process的问题

来源：百度知道 编辑：UC知道 时间：2024/09/22 20:18:39
小弟现要把一段Verilog的程序转成vhdl，用的是X-hdl软件，
always@(negedge clock or posedge reset)
begin
if(reset) cnt <= 6;
else
if(cnt >= 5)
cnt <= 0;
else
cnt <= cnt + 1;
end

转出来后是
PROCESS
BEGIN
WAIT UNTIL (clock'EVENT AND clock = '0') OR (reset'EVENT AND reset = '1');
IF (reset = '1') THEN
cnt <= "110";
ELSE
IF (cnt >= "101") THEN
cnt <= "000";
ELSE
cnt <= cnt + "001";
END IF;
END IF;
END PROCESS;
报的错是
Error (10628): VHDL error at control_vhd.vhd(81): can't implement register for two clock edges combined with a binary operator
我的理解是一个2个时钟的沿不能再一个wait until 中，小弟稍稍懂一点，于是改了改
PROCESS( clock,reset )
BEGIN
if( reset = '1' ) then

process(clk,reset)
begin
if reset='1' then cnt<="110";
elsif clk'event and clk='0' then
if cnt>="101" then cnt<="000";
else cnt<=cnt+'1';
end if;
end if;
end process;

process (clock, reset)
if (rst) = '1' then
cnt <= "0110";
elsif (clock'event and clock = '0') then
if((cnt = "0101") or (cnt > "0101"))then
cnt <= "0000";
else
cnt <= cnt + '1';
end if;
end if;
end process;

一个进程中最好不要检测两个边沿信号，你把你clock写成边沿检测，复位电平检测看下